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Everest Processor

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Everest Processor

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Everest Processor

News

Pipelined version of Everest core

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Hi! We are develop popelined version of our core. Would you like to be first who have seen modulation results? Here is screenshot of waves at the moment of successful test completion. Let us explain what is going on this picture. These waves are produced by last iteration of following a...
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Welcome to the site of EVEREST processor!

What is it? It is brand new architecture of central processor unit. Our ISA pretend to be very extensible, have a good code density, and support multitasking at hardware level. Who are we? We are team of hardware and software enthusiasts and this project is our hobby. Why do we need new...
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Blog

Current status

The screenshot shows the moment of debugging the pipelined kernel of processor “Everest”. We build a model using the ModelSim software. Waves in the screenshot correspond to the execution of the following code section: This code is typical for example on the initialization of list....
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Instruction to an instruction set

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We have created the instruction set map, putting all instructions implemented in the processor to 16×16 sized table. The first line is a single-byte instructions. The third line – two byte instructions. Reserved operation codes have yellow background in the table (picture is...
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